A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators
Hiroyuki Mizuno, Nozomu Matsuzaki, Kensuke Osada, T. Shinbo, Nagatoshi Ohki, H. Ishida, K. Ishibashi, T. Kure · IEEE Journal of Solid-State Circuits · 1996
A 1-V 16-KB (L2) 2-KB (L1) four-way set-associative cache was fabricated using a 0.25-/spl mu/m CMOS technology for future low-power high-speed microprocessors. Effective latency of 6.9 ns and power consumption of 10 mW at 100 MHz are obtained at a supply voltage of 1 V. This performance is achieved by using a new separated bit-line memory hierarchy architecture (SBMHA) that speeds up latency and reduces power consumption, and domino tag comparators (DTC's) that reduce the power dissipation of tag comparisons.