Architecture for simulation system with consideration of circuit partition
N. Tanaka, Hideki Asai · 1991
A description is presented of a circuit simulation system with the dedicated parallel processor SMASH. This system performs model evaluation and LU decomposition, etc., independently at the host computer and SMASH. As a result, it is shown that the simulation time can be reduced to the element model evaluation time. It is also shown that this system is available in case the matrix solution time is dominant over the total simulation time.>