A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits
T. Hosokawa, H. Date, Michiaki Muraoka · 2003
This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.