Formal semantics of VHDL for verification of circuit designs
G.X. Hua, H. Zhang · 2002
Despite of the recent progress on formal verification of circuit designs, there exists a big gap between the hardware designers and the people who conduct formal verification (called verifiers), because of the lack of common specification languages. To solve this problem, we choose VHDL, a standard hardware design language, and enrich it properly so that the designer and the verifier has a unified platform to design and verify circuits. We develop a denotational semantics for (a significant subset of) VHDL, and based on this semantics we implement a prototype translator which automatically translates VHDL into logic formulas. We have used this translator and a theorem prover for formally verifying both combinatorial and sequential (synchronous) circuits written in VHDL.>