CMOS customer implementation of the SPARC architecture
Masood Namjoo, F. Abu-Nofal, Doug Carmean, R. Chandramouli, Yu-Chuan Chang, J. Goforth, W. Hsu, R. Iwamoto, C.W. Murphy, U. Naot, Michael Parkin, Joan M. Pendleton, Caitlin Porter, J. Reaves, R. Sindhu Reddy, Garry Swan, D. Tinker, Po Tong, Lawrence Yang · 1988
Using custom circuitry, a higher level of performance has been achieved for a new implementation of the Scalable Processor Architecture (SPARC). A CY601 processor (integer unit), running at a clock rate of 25-33 MHz, implements the complete set of SPARC instructions in a 0.8- mu m CMOS technology. An overview is given of the processor chip and its interface to the external cache, floating-point unit, and a generic coprocessor.>