Embedded high-speed BCH decoder for new-generation NOR flash memories
Xueqiang Wang, Dong Wu, Chaohong Hu, Liyang Pan, Zhou Runde · 2009
A high-speed double-error-correcting (DEC) BCH decoder for new-generation NOR flash memory is presented to improve reliability. To speed up the decoding process, a multiplication-free linear transform is developed to eliminate iterations and divisions in Galois fields. Furthermore, a reverse data-flow analysis (RDFA) and smoothest descent approach are proposed to reduce latency in the bit-parallel Chien search. Based on peripheral 180 nm CMOS process, the whole BCH decoder is designed and the latency is significantly reduced to less than 5 ns.