A 100MHz hardware-efficient boost cascaded face detection design
Wei-Su Wong, Chih‐Rung Chen, Ching‐Te Chiu · 2009
In this paper, we present a novel face detection architecture based on the boosted cascade algorithm. A reduced two-field feature extraction scheme for integral image calculation is proposed. Based on this scheme, the required memory for storing integral images is reduced from 400Kbits to 2.016Kbits for a 160×120 gray scale image. The range of the feature size and location is also reduced so the learning time of the classifier decreases around 10%. In addition, input data are mapped into parallel memories to enhance processing speed in classifier evaluations. This boosted cascade face detection hardware consumes only 0.992 mm2under the UMC 90 nm technology and runs at 100 MHz. The experimental results show this face detector can achieve 91% face detection rate for processing 160×120 gray scale images at the speed of 190 fps.