Efficient FPGA-Based Realization of Complex Squarer and Complex Conjugate using Embedded Multipliers
Shuli Gao, D. Al-Khalili, Noureddine Chabini, Pierre Langlois · 2006
This paper presents an efficient design methodology and a systematic approach for the implementation of squaring of complex numbers and their conjugate, using small-size embedded multipliers. Various benchmarks were tested for operands with size ranging from 19 to 85 bits targeting Xilinx Spartan-3 FPGA. Our proposed approach was compared with the traditional technique. The results illustrate that our design approach is very efficient in terms of timing and area saving. For the complex squarer, the combinational delay is reduced by an average of 16.8% and area saving, in terms of 4-inputs LUTs, is about 27.2%. For the complex conjugate realization, combinational delay and area are reduced by about 18.6% and 41.6%, respectively.