A 1 V heterogeneous reconfigurable processor IC for baseband wireless applications
H. Zhang, Vandana Prabhu, Varghese George, M. Wan, M. Benes, Arthur Abnous, Jan M. Rabaey · 2002
The Pleiades processor approach combines an on-chip microprocessor with an array of heterogeneous programmable computational units of different granularities (called satellite processors) connected by a reconfigurable interconnect network. The microprocessor supports the control-intensive components of the applications as well as the reconfiguration, while repetitive and regular data-intensive loops (called kernels) are directly mapped on the array of satellites by configuring the satellite parameters and the interconnections between them. Synchronization between the satellite processors is by a data-driven communication protocol in accordance with the data-flow nature of the computations performed in the kernels. A generalized interface wrapper is placed around each satellite processor to comply with the communication protocol. This spatial programming approach results in energy efficiency levels of 50-100 MIPS/mW, at least an order of magnitude better than what can be accomplished in comparable DSP processors, by exploiting the locality of the computations and the correlations within data streams, and by distributing the control.