An Optimum FIR Filter Implementation For Color Signal Decimation In SD-DVCR System Using FPGA
Sung‐Hoon Kim, H.W. Park, Se-Yong Ro, Y Lim, Gwang-Chul Park, Ki‐Doo Kim · International Conference on Consumer Electronics · 1997
This paper describes the realization of a color decimation filter programmed in VHDL and AHDL to reduce color signal sampling rate in SD-DVCR system using FPGA. We apply the Remez exchange algorithm to estimate the coefficients of an optimum FIR filter. For the color decimation filter, we propose a pipelined architecture to improve computational speed and apply symmetric taps to reduce the circuitry required to implement linear phase FIR filter.