Architecture for VLSI design of CA based byte error correcting code decoders
Debashish Chowdhury, P.P. Chaudhuri · 2002
This paper reports a novel architecture for byte error correcting code decoders using Cellular Automata (CA). The chip architecture of the basic building blocks for double byte error locating/correcting code (DbEL/DbEC) is presented. Extension of the architecture to detect arbitrary number of byte errors has also been included. The proposed decoder provides a simple, modular, cascadable and cost effective design that is ideally suited for VLSI implementation.>