Xtensa with user defined DSP coprocessor microarchitectures
G. Ezer · 2002
This paper describes the third generation configurable and extensible Xtensa/sup TM/ processor with enhanced DSP functionality targeted to System-On-Chip (SOC) designs. Xtensa III processor family can be configured with an IEEE-compatible floating point unit (FPU) and/or a powerful, energy efficient Vector Integer coprocessor, both implemented using Tensilica Instruction Extension (TIE) language and automatically integrated with the Xtensa base processor core.