A Two-Dimensional Superscalar Processor Architecture
Sascha Uhrig, Basher Shehan, Ralf Jahr, Theo Ungerer · 2009
This paper proposes a new processor architecture optimized for execution of sequential instruction streams. The architecture, called Grid Alu Processor (GAP), comprises an in order superscalar pipeline front-end enhanced by a configuration unit able to dynamically issue dependent and independent standard machine instructions simultaneously to the Arithmetic Logic Units (ALUs) organized in a two-dimensional array. In contrast to well-known coarse-grained reconfigurable architectures no special synthesis tools are required and no configuration overhead occurs. Simulations of the GAP show a maximum Instructions Per Cycle (IPC) speedup of about 2.56 compared to the results of an equivalently configured SimpleScalar processor simulator.