A strategy for avoiding pipeline interlock delays in a microprocessor
T. Yoshida, M. Matsuo, T. Ueda, Yuichi Saito · 2002
Pipelining of instruction execution significantly improves computer performance, but high dependencies between instructions limit the maximum concurrency that is achievable by pipelining. A hardware scheme to avoid pipeline interlock delays caused by dependencies in address generation is proposed. This scheme is implemented in the 32-b microprocessor M32/100. The M32/100 has a hardware interlock mechanism with scoreboard registers and a working stack pointer that is modified prior to the execution of each instruction. A simulator has been written and several benchmarks have been executed to investigate the performance achieved by these schemes.>