A 2.97 Gb/s DPA-resistant AES engine with self-generated random sequence
Po-Chun Liu, Ju-Hung Hsiao, Hsie-Chia Chang, Chen‐Yi Lee · 2011
This paper presents a DPA-resistant AES crypto engine. The DPA countermeasure circuit is combined with a self-generated random number generator to eliminate an extra circuit for generating random bits. The cell area for the DPA-resistant AES crypto engine is 0.104 mm2in UMC 90 nm CMOS technology, which is only 6.2% larger than an unprotected AES engine. The maximum operating frequency of the AES engine is 255 MHz, resulting in 2.97 Gb/s throughput. Since the DPA countermeasure circuit works in parallel with the AES engine, no throughput degradation is incurred with the proposed architecture. The proposed DPA-resistant AES engine has significant improvements over previous state-of-the-art designs.