Compiler Optimization on Instruction Scheduling for Low Power
Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi‐Chun Tsai · 2000
In this paper, we investigate the compiler transformation techniques to the problem of scheduling VLIW instructions aimed to reduce the power consumption on the instruction bus. It can be categorized into two types: horizontal and vertical scheduling. For the horizontal case, we propose a bipartite-matching scheme. We prove that our greedy algorithm always gives the optimal switching activities of the instruction bus. In the vertical case, we prove that the problem is NPhard, and propose a heuristic algorithm. Experimental results show average 13% improvements with 4way issue architecture and average 20% improvement with 8-way issue architecture for power consumptions of instruction bus as compared with conventional list scheduling for an extensive set of benchmarks. 1 Introduction The push for low power design has recently gained growing importance in designing various computer systems and embedded systems. For that reason, we will study the aspect of compiler transformations to red...