A serial interfacing technique for built-in and external testing of embedded memories
Benoit Nadeau-Dostie, Allan L. Silburt, V.K. Agarwal · 1989
A description is presented of a serial interfacing technique for embedded RAMs, which has been successfully applied to static single-port and dual-port memories in custom integrated circuits. A single bit of the input data path of a RAM (or a group of RAMs) is controlled by the built-in self-test (BIST) circuit, and a single bit of the output data path is observed during the execution of the algorithms. The other bits are controlled and observed indirectly through the serial data path. Automatically generated BIST circuits, which embed an algorithm suited for the application with the RAM, have been developed. The serial data path interface has also been used to provide external access to memories on cost sensitive chips which could not justify the full BIST overhead. This provides a simple external test access mode which uses a minimal number of pins yet exercises the memory at full speed