A high speed FIR filter designed by compiler
Richard I. Hartley, Peter F. Corbett, Paul Jacob, S. Karr · 1989
Digital-serial computation is a hybrid between bit-serial computation and parallel computation. In digit-serial computation, data is divided into digits ofNbits, and computations take place one digit of data at a time. The PARSIFAL silicon compiler is a software environment for designing chips using this basic computational architecture. The authors report on a four-tap FIR (finite-impulse response) filter built using this compiler. In order to avoid the throughput loss inherent in serial computation, two parallel computations are interleaved to achieve a 35-MHz-per-sample throughput rate