Debug of the CELL Processor: Moving the Lab into Silicon
M. Riley, Nathan Chelstrom, Mike Genden, Shoji Sawamura · Proceedings/Proceedings - International Test Conference · 2006
With 234 million transistors, making up 9 processing units and 3 asynchronous clock domains in a high speed design, the CELL processor clearly presents a challenge to debug work required during lab bring-up and test bring-up. Traditional multi-processing systems reap the benefit of standard system level debug practices, but as the system has moved into the silicon so must the access during bring-up. This paper explains some of the innovative debug features included in the CELL processor design that were critical for efficient bring-up in a limited access environment