A video signal processor for motion-compensated field-rate upconversion in consumer television
P.E.R. Lippens, B. De Loore, Geert de Haan, Peter A. Eeckhout, Henk Huijgen, A. Loning, Brian McSweeney, M. Verstraeien, B. Pahn, Jeroen Kettenis · IEEE Journal of Solid-State Circuits · 1996
An IC for 100-Hz television has been realized implementing motion estimation and compensation algorithms for high-quality upconversion and a judder-free motion portrayal of movie material. The four embedded video signal processors on this IC provide a processing power of 10 giga-operation per second (GOPS). Their architecture was generated from an algorithm description using behavioral synthesis. The required 25-Gb/s memory bandwidth was realized by embedding 24 single/dual port SRAM/DRAM instances. The test approach includes full scan, boundary scan, functional testing, built-in-self-test, and IDDq-test. The so-called "Natural Motion" feature implemented by this IC was demonstrated at the IFA'95 and received the European Video Innovation Award 95-96.