Integrating formal verification in an online judge for e-Learning logic circuit design
Javier de San Pedro, Josep Carmona, Jordi Cortadella, Jordi Petit · 2012
This paper investigates the use of formal verification techniques to create online judges that can assist in teaching logic circuit design. Formal verification not only contributes to give an exact assessment about correctness, but also saves the instructor the tedious task of designing test cases. The paper explains how formal verification has been integrated in an online judge. It also describes the courseware created for a course on logic circuits and the successful experience of using it in a one-week summer course with students from secondary and high school.