A unified DCT/IDCT architecture for VLSI implementation
J. Parkhurst, K.W. Current, A.K. Jain, J.E. Grishaw · 2003
A unified discrete cosine transform/inverse discrete cosine transform (DCT/IDCT) architecture suitable for VLSI implementation is presented. A single VLSI NMOS chip design and layout for realizing this architecture is described. Algorithm simulations and experimental performance of integrated test subcircuits indicate that this chip would be capable of real-time processing of 10-MHz video signals. It is considered that circuits of this type could be very useful in real-time image data compression.>