Performance driven bus buffer insertion
Chia‐Chun Tsai, De-Yu Kao, Chung‐Kuan Cheng · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1996
In this paper, we propose a heuristic algorithm for a given topology of a multisource multisink bus to reduce the signal delay time. The algorithm minimizes the delay by inserting buffers into the candidate locations and sizing the buffers. When compared with the traditional method of source driver sizing, experiments show up to 7.2%, 20.7%, and 29.6% improvement in delay for 2.0, 0.5, and 0.3 /spl mu/m technologies, respectively.