Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test
Sobeeh Almukhaizim, Ozgur Sinanoglu · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2009
Scan chain partitioning techniques are quite effective in reducing test power, as the rippling in the clock network, scan chains, and logic is reduced altogether. Partitioning approaches implemented in a static manner may fail to reduce peak power down to the desired level, however, depending on the transition distribution of the problematic pattern in the statically constructed scan chain partitions. In this paper, we propose a dynamic partitioning approach capable of adapting to the transition distribution of any test pattern and, thus, of delivering near-perfect peak power reductions. The proposed dynamic partitioning hardware allows for the partitioning reconfiguration on a per test pattern basis, hence delivering a solution that istestsetindependent, yet its quality is superior to that of any test set dependent solution.