Associative massively parallel computers
R.M. Lea, I.P. Jalowiecki · Proceedings of the IEEE · 1991
Associative processing architectures as candidates for second-generation massive parallel computers (MPCs) are discussed. The authors outline the principle of operation of associative processors, and briefly review their development. They explore the associative string processor (ASP) architecture as a representative case study in the development of a second-generation MPC.>