Reconfiguring fault-tolerant two-dimensional array architectures
N.J. Davis, F.G. Gray, J.A. Wegner, S.E. Lawson, V. Murthy, Tennis S. White · IEEE Micro · 1994
Circuit complexities reduce overall reliability and mean-time-between-failure rates of today's very large processing arrays. Our integrated, three-level hierarchy of reconfiguration methods provides reasonable levels of fault tolerance for such systems. Operating in a completely distributed fashion, the hierarchy does not require that any components be fault free. It significantly improves array reliability by using a combination of transient fault rollback techniques and local and global reconfiguration algorithms.>