Charge sharing fault analysis and testing for CMOS domino logic circuits
Ching-Hwa Cheng, Wen-Ben Jone, Jinn‐Shyan Wang, Shih-Chieh Chang · 2002
Because domino logic design offers smaller area and faster delay than conventional CMOS design, it is very popular in the high-performance processor. However, domino logic suffers from several problems and one of the most notable ones is the charge sharing problem. In this paper, we describe a method to measure the sensitivity of the charge-sharing problem for each domino gate. In addition, our algorithm also generates test vectors to detect the worst case of charge-sharing fault.