4-way superscalar DSP processor for audio codec applications
Joon Seok Kim, Sun Kook Yoo, Sung Wook Park, Nam-Hoon Jung, Woo-Suk Ko, Keum Sup Lee, Dae Hee Youn · 2002
Audio codec (coding/decoding) algorithms are complex, of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor: YSP-3, operates four functional units (multiplier, two ALUs, load/store unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the common DSP algorithms and the AC-3 decoder.