FPGA implementation of high speed multiplierless frequency response masking FIR filters
Yong Lian · 2002
This paper presents the design and implementation of high speed, multiplierless, narrow transition width FIR filters using FPGA. The narrow transition width FIR filters are realized by using modified frequency response masking structure which improves the throughput rate by replacing long length filter in the original frequency response masking approach with 2 or 3 cascaded short length filters.