An Ultra-high Speed Public Key Encryption Processor
Peter A. Ivey, Simon N. Walker, J.M. Stern, Simon Davidson · 1992
This paper describes the architecture and design of a public key encryption processor which implements the RSA algorithm with key lengths of512 bits. The chip, which is 6.2 by 4.2 millimetres, has been designed in a 0.7 micron CMOS, silicon on insulator process and has a target clock speed of 15OMHz. It is a self contained subsystem which interfaces directly to standard microprocessors and will be capable of encrypting at rates well in excess of 64k baud (for contractural reasons we are unable, at this time, to disclose the emct speed of operation).