A 1.8-ns random cycle SRAM-interface High-speed DRAM (SH-RAM) compiler with Data Line Replica Architecture
Naoki Kuroda, Naoki Yamada, Toshihiro Nakamura, Yoshihiko Sumimoto, Masanobu Hirose, Kiyoto Ohta, Y. Agata, Yuji Yamasaki, Hironori Akamatsu · 2008
The SRAM-interface High-speed DRAM (SH-RAM) is an embedded DRAM that can replace almost all embedded SRAMs in SoC fabricated by a 65-nm LSTP embedded DRAM process. This paper describes the SH-RAM compiler that realizes a 1.8-ns random cycle time and a 1.5-ns random access time at 512-Kb macro without area penalty by High-speed Bit Line Operation and Data Line Replica Architecture.