CMOS bilateral linear floating resistors for neural-type cell arrays
Louiza Sellami, Sandeep Kumar Singh, R.W. Newcomb, Angela Rasmussen, Mona Elwakkad Zaghloul · 2002
A previous CMOS bilateral linear resistor is modified into two different configurations of floating resistors using the structure of a two-transistor CMOS bilateral linear resistor in the first configuration and two two-transistor CMOS bilateral linear resistors and current mirrors in the second configuration. Simulation results using parameters of MOSIS transistors are presented to verify the theory. These floating resistors can be used for coupling weights in VLSI neural-type cell arrays.