New serial architecture for the Berlekamp-Massey algorithm
Hsie-Chia Chang, C.B. Shung · IEEE Transactions on Communications · 1999
We propose a new efficient serial architecture to implement the Berlekamp-Massey (1968, 1969) algorithm, which is frequently used in BCH and Reed-Solomon (1960) decoders. An inversionless Berlekamp-Massey algorithm is adopted which not only eliminates the finite-field inverter but also introduces additional parallelism. We discover a clever scheduling of three finite-field multipliers to implement the algorithm very efficiently. Compared to a previously proposed serial Berlekamp-Massey architecture, our technique significantly reduces the latency.