A performance evaluation of 2D-mesh, ring, and crossbar interconnects for chip multi-processors
Jesús Camacho Villanueva, José Flich, José F. Duato, Hans Eberle, Nils Gura, Wladek Olesinski · 2009
As the number of processing nodes on chip multi-processors (CMPs) keeps increasing, providing efficient communication with the on-chip interconnect becomes increasingly critical. With 32-core CMP designs on the drawing table of engineers, there is a demand for accurate simulation models that capture all the complexities and interactions of the different design layers including the application, operating system, cache hierarchy, coherency protocol, and other on-chip resources. These components cannot be modeled anymore in isolation as unpredicted performance anomalies may arise once all the system variables are taken into account.