ASIP decoder architecture for convolutional and LDPC codes
Steffen Kunze, Emil Matúš, Gerhard Paul Fettweis · 2009
In this paper we present a multi-mode decoder architecture for convolutional codes and structured low-density parity-check (LDPC) codes based on a novel computation unit that is able to process Min-Sum as well as Add-Compare-Select (ACS) operations. Realized as application-specific instruction set processor (ASIP), this allows decoding of a vast number of different channel codes and implementation of various communication standards' channel coding schemes with just one single IPcore. Implemented in 130 nm technology, this results in a Viterbi decoding throughput of 30 Mbit/s at 200 MHz for an area of 745 kGates and power consumption of 130 mW.