Multi-output one-digitizer measurement
S. Sasho, M. Shibata · 2002
Reducing test costs is a constant issue for semiconductor manufacturers. One key to reducing test cost is reducing test time. Parallel testing is widely employed for this purpose, but the cost of the parallel test system itself is generally high, and simpler test systems would bring further substantial reductions in test cost. We have developed test system structures in which the number of digitizers is much smaller than the number of device functions being tested, as a means of reducing the cost of the parallel test system. Here we describe three of these test system configurations and an investigation of their performance in parallel testing of one or two two-channel mixed-signal devices. The results demonstrate the possibility of relatively low-cost, efficient parallel testing of two or more two-channel DACs with one digitizer, based on a mixed-signal tester currently in general use.