Hierarchical self-test concept based on the JTAG standard
J. Maierhofer · 2002
The author describes the concept and setup of a hierarchical self-test architecture, which includes the entire system, module, device, and macrocell levels. The concept is based on a hierarchy of controllers, which control the self-test on each level. Between the levels, test buses are used for transporting test information. The self-test architecture is explained in detail at the device and macrocell levels. The IEEE Std. 1149.1 aimed at by JTAG (Joint Test Action Group) forms the test interface between the device and the module.>