A Fast Optimal Robust Path Delay Fault Testable Adder
Bernd Becker, Rolf Drechsler, Rolf Krieger, Sudhakar M. Reddy · 1996
In this paper we explore the test complexity of the adder function with respect to the robust path delay fault model. A lower bound of# n 2 # for the cardinality of a complete test set for a combinational n-bit adder is proven. This result is valid for any adder design known until now. In addition we present a fast O# p n#-time adder that is fully robust path delay fault testable with a test set of size ##n 2 #. 1 Introduction Even if chips are correctly designed, a non negligible fraction of them will havephysical defects caused by imperfections occurring during the manufacturing process #e.g., open connections induced by dust particles #. Therefore, there has to be a test phase in which `production' veri#cation is performed, i.e., in which the `good' chips are sorted from the `bad' ones. For a detailed treatment of the topic see #2#. Due to the variety of possible defects restrictions on a subset of the possible faults are necessary; these simplifying assumptions based on exp...