Accurate Rank Ordering of Error Candidates for Efficient HDL Design Debugging
Tai-Ying Jiang, C.-N.J. Liu, Jing-Yang Jou · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2009
When hardware description languages (HDLs) are used in describing the behavior of a digital circuit, design errors (or bugs) almost inevitably appear in the HDL code of the circuit. Existing approaches attempt to reduce efforts involved in this debugging process by extracting a reduced set of error candidates. However, the derived set can still contain many error candidates, and finding true design errors among the candidates in the set may still consume much valuable time. Adebuggingprioritymethod was proposed to speed up the error-searching process in the derived error candidate set. The idea is to display error candidates in an order that corresponds to an individual's degree of suspicion. With this method, error candidates are placed in a rank order based on their probability of being an error. The more likely an error candidate is a design error (or a bug), the higher the rank order that it has. With the displayed rank order, circuit designers should find design errors quicker than with blind searching when searching for design errors among all the derived candidates. However, the currently used confidence score (CS) for deriving thedebuggingpriorityhas some flaws in estimating the likelihood of correctness of error candidates due to themaskingerrorsituation. This reduces the degree of accuracy in establishing adebuggingpriority. Therefore, the objective of this work is to develop a new probabilistic confidence score (PCS) that takes themaskingerrorsituation into consideration in order to provide a more reliable and accuratedebuggingpriority. The experimental results show that our proposed PCS achieves better results in estimating the likelihood of correctness and can indeed suggest adebuggingprioritywith better accuracy, as compared to the CS.