A single-chip MPEG-2 codec based on customizable media microprocessor
Shunichi Ishiwata, Tomoo Yamakage, Y. Tsuboi, Takayoshi Shimazawa, T. Kitazawa, S. Michinaka, K. Yahagi, Hideo Takeda, A. Oue, Tetsuya Kodama, Nobu Matsumoto, Takayuki Kamei, Takashi Miyamori, G. Ootomo, M. Matsui · 2003
A single-chip MPEG2 MP@ML codec, integrating 3.8M gates on a 72mm/sup 2/ die, is described. It has a heterogeneous multiprocessor architecture in which six microprocessors with the same instruction set but different customization execute specific tasks such as video, audio etc. concurrently. The microprocessor, developed for digital media processing, provides various extensions such as a VLIW one and a DSP one inherent in its architecture. Making full use of the extensions, the chip executes encoding and decoding of video, audio and system concurrently in real time.