Full systolic binary multiplier
J. Arechabala, Eduardo Boemo, Juan Meneses, Félix Moreno, Carlos Alberto López Barrio · IEE Proceedings G Circuits Devices and Systems · 1992
The paper describes the architecture of a binary multiplier that, because of its intrinsic regularity and simplicity, may be extended for any number of bits. It is a modification of the array of full adders scheme, which allows the operation with two's complement numbers in systolic mode. The design has been validated and implemented in the SOLO 1400 environment, using ES2 standard cells. Laboratory prototypes perform a multiplication every 24 ns. Finally, a preliminary evaluation of a full custom version is presented.