Performance Comparison of RS Decoder on Family of MAX CPLD using Verilog HDL
Hitesh G Kamani · PARIPEX-INDIAN JOURNAL OF RESEARCH · 2012
In this paper design of Reed Solomon (255,239) Decoder and perform this decoder on family of MAX CPLD and compare the performance based on area occupied by the design and the speed at which the design can run and power dissipation. I applied forward error correction system to improve the overall performance of the system .The implementation is Written in Verilog HDL based on Barlekamp Massy, Forney and Chien Search Algorithm.