C/sup 3/L: a chip for connected component labeling
A. Rasquinha, Meghna Ranganathan · 2002
Connected component detection and labeling is an essential step in many image analysis techniques. In this paper, we propose a systolic VLSI architecture for labeling connected components in an image. The architecture has been designed and verified using Cadence Verilog-XL and also implemented on a rapid prototyping system using FPGA's connected as a linear systolic array. Although, the algorithm has a time complexity of O(N/sup 2/), this is in term of the actual clock cycle which is 15 ns. The proposed hardware can process a 128/spl times/128 image in 0.992 ms and uses 128 processors whereas the MPP requires 94.6 ms with 16384 processors.