An efficient gate re-assignment algorithm in post technology mapping
Tzu-Hsi Pan, Chin‐Long Wey · 2002
Inverter pairs are generally inserted to all internal nodes of a network to increase the flexibility of mapping the subject network onto the library gates, but it also increases the number of unwanted inverters in the mapped networks. Thus, inverter minimization can be used during or after technology mapping to reduce the unwanted inverters and to further improve the quality of the mapped network. In this paper, an efficient gate re-assignment algorithm, GRASS, is presented for inverter and area minimization in post technology mapping. Minimization is achieved by re-assigning a gate to its NPN equivalent gate to reduce the number of inverters and/or to use a smaller NPN equivalent gate. Experimental results show that GRASS achieves 6% of area improvement and 8% of delay improvement for MCNC benchmark circuits. GRASS also achieves more than 25% of inverter reduction over that in sis-1.2.