A correlation matrix method of clock partitioning for sequential circuit testability
Yong Chang Lim, Vishwani D. Agrawal, K.K. Salnja · 2003
We propose a method of partitioning the set of all flip-flops in a circuit for multiple clock testing. In the multiple clock testing, flip-flops are partitioned into different groups and each group of flip-flops has an independent clock control. In our method, we use a test generator assuming an independent clock control for each flip-flop. We than determine correlation between clock activity for all pairs of flip-flops. This information is then used to an optimal or near optimal partition of flip-flops in the circuit. Through experiments, we demonstrate that our partitioning method increases fault coverage and reduces test length with almost no hardware overhead or performance penalty.