VLSI implementation of decoder for decompressing fractal-based compressed image
Kyung-Hoon Kim, Chang-Yu Hong, Lee‐Sup Kim · 2002
This paper presents an efficient architecture for decompressing fractal-based compressed images and its VLSI implementation with high decoding speed and low hardware cost. The chip is fabricated using 5 V, 1 poly 3 metal, 0.6 /spl mu/m CMOS technology. The proposed VLSI architecture uses the Modified Recursive Decoding Algorithm (MRDA), which reduces the number of iterations and hardware areas. The proposed decoder architecture shows that RAM size is reduced by 50% and the decoding speed to get final attractor (reconstructed image) is improved by 50%, compared with conventional method using Classical Recursive Decoding Algorithm(CRDA). Based on the operating frequency(50 MHz), the decoder can produce about 70-80 image frames(256/spl times/256) per second. Therefore, it can decode 2-D quadtree partitioned fractal images in real time.