A 2 Gb/s balanced AES crypto-chip implementation
F. K. Guürkaynak, Andreas Peter Burg, N. Felber, Wolf Fïchtner, D. Gasser, F. Hug, Hubert Kaeslin · 2004
We present a balanced 2 Gb/s en-/decryption ASIC realization of the AES algorithm that supports all standard operation modes and key lengths. Rather than optimizing only for throughput, special care is taken to balance the more involved decryption path with that of the encryption path using a number of high-level architectural and register transfer level optimizations. The fabricated en-/decryption core requires an active area of only 3.56 mm2 (less than 120,000 gate equivalents) in a modest 0.25 µm CMOS technology.