Automatic Testbench Generation for Rearchitected Designs
Mark H. Nodine · 2007
This paper describes a tool for automated testbench generation used to compare a design against a cycle-accurate RTL reference model. The advantage of this tool is that it allows testing of design modules as they become ready, using chip-level test suites or random tests. The tool is able to handle arbitrary encodings of RTL signals to design signals, retiming, and even changes to the module boundaries.