Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems
Kazuhiro Nakamura, Masatoshi Yamamoto, Kazuyoshi Takagi, Naofumi Takagi · 2008
In the paper, we present a new fast and memory efficient VLSI architecture for output probability computations of continuous Hidden Markov Models (HMMs). The computations are the most time-consuming part of HMM-based recognition systems. High-speed VLSI architectures for the computations with small register size and low-power dissipation are required for the development of mobile embedded systems capable of sophisticated human interfaces. We show stored-based block parallel processing (StoredBPP) for the output probability computations, and present a VLSI architecture for StoredBPP. Compared to the conventional stream-based block parallel processing (StreamBPP) based architecture, the proposed architecture requires less registers, less processing elements and less processing time, when the number of HMM states is large for the accurate recognition.