A Path Delay Fault Simulator for Sequential Circuits
Soumya Bose, Rahul Agrawal, Vishwani D. Agrawal · 2005
To analyze path delay faults in synchronous sequential circuits, stimuli are simulated in a dual-vector mode. The signal states represent the logic and transilion conditions for two consecutive vectors. APer the simulation of each vector, only the activated paths are traced and the corresponding fault effect, if propagated to a flipflop, is added to its fault list. A path numbering scheme avoids storage of path data which can be generated, if needed, from the path number. The differential fault simulation technique is used to propagate the stored fault effects of previously activated paths. The simulation is independent of the specific delays of the combinational elements and either robust or nonrobust detection can be simulated as an option to the user. However, considering sequential robustness, a path delay fault should be testable irrespective of the delays of all other paths. In that sense, our present version simulates only non-robust faults. Ezperimental results on ISCAS '89 sequential benchmarks using the test patterns generated by a recently published 0.2gorithm verify the effectiveness of the simulator.